More performance is being demanded of semiconductor memory devices such as DRAMs and SRAMs, by processors used for high powered PC and workstation systems, as well as by cache and graphics subsystems and high speed communications equipment. A rapidly growing classification of fast memory architecture is the synchronous memory. Making a memory synchronous puts it under the control of a system clock. "Wait states", during which a processor must wait for output data from the memory, can be reduced or eliminated using synchronous control. In systems with synchronous memory, input addresses can be latched into the memory, freeing a processor to perform other tasks until data is available after a predetermined number of cycles. While the intrinsic speed of a memory does not increase with the addition of a synchronous interface, the overall effective speed of the system increases because waiting time is reduced. Another advancement of the synchronous memory is its ability to synchronously burst data at a high-speed data rate.
Many synchronous memories also come with programmable features, such as a programmable column address strobe (CAS) latency period. The term "CAS latency" refers to a time interval which is measured from an active edge point of the CAS signal to a point in time when an output is generated in response to the CAS signal. For example, if a CAS latency of two clock cycles is programmed, then data will be output one clock cycle after a read command has been received. However, if a CAS latency of three clock cycles has been programmed, then data will be output two clock cycles after a read command has been received. Accordingly, the CAS latency determines the clock cycle at which data will become available after a read/write command has been provided. The CAS latency is also typically unaffected by clock rate.
As will be understood by those skilled in the art, depending on the frequency, data can be made available at an output buffer as early as one clock cycle less than the CAS latency. Generally, a CAS latency of one (1) can be programmed for clock rates below 33 MHZ, a CAS latency of two (2) can be programmed for clock rates ranging from 34 to 67 MHZ, and a CAS latency of three (3) can be programmed for clock rates ranging from 68 to 100 MHZ or above.
Referring now to FIG. 1, a conventional synchronous memory device capable of utilizing different CAS latency modes of operation is illustrated in block diagram form. The synchronous memory includes a memory cell array 10, a mode register 11, a column address buffer 12, a column pre-decoder 13, a main column decoder 14, a block sense amplifier (BLSA) and input/output (I/O) gate circuit 15, a write enable buffer 16, internal clock generators 17, 18 and 19, a CSL timing controller 20, an I/O sense amplifier 21, and a data output buffer 22.
Memory cell array 10 consists of an array of memory cells arranged in rows and columns. The mode register 11 stores the data for controlling the various operating modes of the synchronous memory. The mode register 11 may be programmed after power-on and before normal operation. In addition, the mode register 11 may also be changed during operation. The "mode register set cycle" may occur while holding a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE low and having present on the address lines the valid mode information to be written into the mode register 11. During operation, the mode register 11 generates a latency state signal CLi (i=1, 2 or 3), which represents a CAS latency of one, two, or three clock cycles, in accordance with the programmed CAS latency period. A column address CA, which is applied to column pre-decoder 13 via column address buffer 12, is decoded.
Using a decoded column address DCA from the pre-decoder 13, the main column decoder 14 generates a column select signal CSL for selecting a column of the memory cell array 10. The column select signal CSL is provided to the block sense amplifier and I/O gate 15, so that data can be sensed, amplified and provided to the data bus DIO. An external clock CLK is also fed to the first internal clock generator 17. The first internal clock generator 17 generates an internal clock signal PCLK which is synchronized to the external clock signal CLK. Write enable buffer 16 generates a write state signal PWR which is also synchronized with the internal clock signal PCLK, in response to an externally applied write enable signal WE. A second internal clock generator 18 receives the latency state signal CLi from the mode register 11 and the write state signal PWR, and generates an internal clock signal FRP which is synchronized with the internal clock signal PCLK. Internal clock generator 19 generates an internal clock signal CLKDQ in synchronization with the external clock signal CLK. A CSL timing controller 20 is fed with the internal clock signal PCLK and generates two control signals CSLE and CSLD to control the timing of the active and inactive edge points of the column select signal CSL. The control signals CSLE and CSLD are synchronized with the internal clock signal PCLK. The I/O sense amplifier 21 senses and amplifies the data on the data bus DIO. After a sensing operation, the amplifier 21 latches the sensed data in response to the internal clock signal FRP and provides the latched data to the data bus DO. The data output buffer 22 latches the data on the data bus DO in synchronization with the internal clock signal CLKDQ. The latched data is outputted onto a data output lead DOUT.
FIGS. 2 and 3 show conventional exemplary circuits for the main column decoder 14 and the CSL timing controller 20 in FIG. 1, and FIGS. 4 and 5 are timing diagrams for describing operations of the conventional synchronous memory device. Referring first to FIG. 3, the CSL timing controller 20 consists of a plurality of inverters electrically connected in series. The CSL timing controller 20 generates control signals CSLE and CSLD by delaying the internal clock signal PCLK. The signals CSLE and CSLD are used to control the active and inactive edge transitions of the column select signal CSL, respectively. It can be seen that the CSLE and CSLD signals have their different delay time periods relative to PCLK, but each signal CSLE or CSLD has a constant delay time period regardless of the timing of the read/write command and the CAS latency period.
Referring now to FIG. 2, the main column decoder 14 includes a NOR logic gate 1, an inverter 2, P-channel MOSFETs 3 and 4, an N-channel MOSFET 5 and a latch 8 consisting of cross-coupled inverters 6 and 7. MOSFETs 3, 4 and 5 have their current conduction paths coupled in series between a power supply voltage V.sub.DD and the ground voltage V.sub.SS. One input terminal of the NOR logic gate 1 receives the control signal CSLE from the CSL timing controller 20 and the other receives the decoded column address signal DCA from column pre-decoder 13. The NOR logic gate 1 provides its output signal to the gate terminals of MOSFETs 3 and 5. The control signal CSLD signal is fed through inverter 2 to the gate terminal of MOSFET 4. The latch 8 is coupled to the junction of MOSFETs 4 and 5 and outputs the column select signal CSL.
Referring now to FIG. 4, in each clock cycle of the external clock signal CLK, the logic 1 CSLD signal pulse is followed by a logic 0 CSLE signal pulse. For example, upon receipt of a column address signal A0 and a write command (i.e., low level WE) during clock cycle CK0, a high level pulse of the internal clock signal PCLK (being synchronized with the rising edge of the clock signal CLK) is produced by the internal clock generator 17. With different delay time periods, a high level pulse of the CSLD signal and a low level pulse of the CSLE signal are then produced in synchronization with the internal clock signal PCLK. Referring again to FIG. 2, when the CSLD and CSLE signals are inactive (i.e., CSLD=0 and CSLE=1), MOSFET 3 is turned on and MOSFETs 4 and 5 are turned off because the decoded column address signal DCA (A0) remains active at a low level throughout the cycle. If the CSLD signal then goes active to a high level, MOSFET 4 will turn on and a low logic signal will be latched by latch 8. As a result, the column select signal CSL from the main decoder 14 will remain at a low logic level. Thereafter, if the CSLE signal goes to an active low level after the CSLD signal has become inactivated at a low level, then MOSFET 5 will turn on so that the latch 8 latches the CSL signal at a high logic level. When this occurs, the main column decoder 14 outputs a high level CSL signal 42. In FIG. 4, the high level CSL signals 42, 44 and 46 correspond to the address signals A0, A1 and A2, respectively. As can be seen, in the subsequent read cycles CK1-CK3, the active and inactive edge points of the CSL signal are controlled by the 1.fwdarw.0 and 0.fwdarw.1 transitions of the CSLE and CSLD signals, respectively.
FIG. 5 shows a timing diagram for the case when the CAS latency is 3 clock cycles. Referring to FIG. 5, in clock cycle CK3, first data D1 is output to the data output lead DOUT. Therefore, a processor can fetch the data in clock cycle CK4 of the clock signal CLK. As can be seen in the figure, pulse signals FRP and CLKDQ are used for latching data in clock cycles CK2 and CK3, respectively. For a CAS latency of 2, the pulse signal FRP should be generated, and for a CAS latency of 3 both pulse signals FRP and CLKDQ should be generated. Accordingly, considering the clock rate ranges (about 34 to 100 MHZ) for CAS latencies of 2 and 3, the timing of pulse signal FRP should be appropriately determined. That is, the active and inactive edge points of pulse signal FRP should be determined so that for both CAS latencies of 2 and 3, first data D1 can be reliably latched by the FRP signal in clock cycle CK2.
However, in the event the programmed CAS latency is 3 cycles and the clock rate is very high (e.g. about or over 100 MHZ), invalid data D2 may appear on the bus DIO early (i.e., the arrival of the data D2 is earlier than that of the CAS latency 2 operation by a time .DELTA.T1) while the FRP signal remains active (i.e., during clock cycle CK3). This is because the active and inactive edge points of the column select signal CSL are determined by the signals CSLE and CSLD, regardless of the CAS latency period, and these signals CSLE and CSLD also dictate the timing of the FRP signal. In such a case, the invalid data D2 may be latched by the I/O sense amplifier 21 and outputted via the data output buffer 22 during clock cycle CK3 instead of the valid data D1.
To solve this problem, a faster FRP signal is needed, but it may not be easy to make the FRP signal faster since its timing in cycle CK2 is controlled by the clock signal CLK. Another approach to the above problem is to delay the active edge point of the CSL signal for read operations, when the CAS latency period is 3. According to this approach, however, high speed read operation with a CAS latency period of 2 is not guaranteed because the first data should be outputted in the cycle CK2 just after the cycle CK1 for synchronizing a read command input.